ARM Cortex-A76: Difference between revisions
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{{Short description|CPU released in 2018}} |
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{{Infobox CPU |
{{Infobox CPU |
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| name = ARM Cortex-A76 |
| name = ARM Cortex-A76 |
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| slow-unit = |
| slow-unit = |
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| fast-unit = |
| fast-unit = |
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| fsb-slowest = |
| fsb-slowest = 100 |
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| fsb-fastest = |
| fsb-fastest = 104 |
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| fsb-slow-unit = |
| fsb-slow-unit = |
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| fsb-fast-unit = |
| fsb-fast-unit = |
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<!-------------------- Cache ---------------------> |
<!-------------------- Cache ---------------------> |
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| l1cache = {{Nowrap|128 [[Kibibyte|KiB]]}} {{Small|({{Nowrap|64 KiB}} [[I-cache]] with parity, {{Nowrap|64 KiB}} [[D-cache]])}} per core |
| l1cache = {{Nowrap|128 [[Kibibyte|KiB]]}} {{Small|({{Nowrap|64 KiB}} [[I-cache]] with parity, {{Nowrap|64 KiB}} [[D-cache]])}} per core |
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| l2cache = {{Nowrap| |
| l2cache = {{Nowrap|128–512 KiB}} per core |
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| l3cache = {{Nowrap|512 |
| l3cache = {{Nowrap|512 KiB–4 MiB}} {{Small|(optional)}} |
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| l4cache = |
| l4cache = |
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| llcache = |
| llcache = |
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| size-from = |
| size-from = |
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| size-to = |
| size-to = |
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| arch1 = [[ARMv8-A]] |
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| microarch = ARM Cortex-A76 |
| microarch = ARM Cortex-A76 |
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| arch = A64, A32, and T32 {{Small|(at the EL0 only)}} |
| arch = [[ARMv8-A]]: A64, A32, and T32 {{Small|(at the EL0 only)}} |
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| instructions = |
| instructions = |
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| extensions = [[ARMv8.1-A]], [[ARMv8.2-A]], Cryptography, RAS, [[ARMv8.3-A]] LDAPR instructions, [[ARMv8.4-A]] dot product |
| extensions = [[ARMv8.1-A]], [[ARMv8.2-A]], Cryptography, RAS, [[ARMv8.3-A]] LDAPR instructions, [[ARMv8.4-A]] dot product |
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The '''ARM Cortex-A76''' is a [[central processing unit]] implementing the [[ |
The '''ARM Cortex-A76''' is a [[central processing unit]] implementing the [[ARMv8.2-A]] 64-bit [[instruction set]] designed by [[ARM Holdings]]' [[Austin, Texas|Austin]] design centre. ARM states a 25% and 35% increase in integer and floating point performance, respectively, over a [[ARM Cortex-A75|Cortex-A75]] of the previous generation.<ref name="anand">{{cite news |last1=Frumusanu |first1=Andrei |title=Arm Cortex-A76 CPU Unveiled |url=https://www.anandtech.com/show/12785/arm-cortex-a76-cpu-unveiled-7nm-powerhouse |accessdate=1 June 2018 |publisher=Anandtech |date=31 May 2018}}</ref> |
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==Design== |
==Design== |
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The Cortex-A76 serves as the successor of the [[ARM Cortex-A73]] and [[ARM Cortex-A75]], though based on a clean sheet design. |
The Cortex-A76 serves as the successor of the [[ARM Cortex-A73]] and [[ARM Cortex-A75]], though based on a clean sheet design. |
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The Cortex-A76 frontend is a 4-wide decode [[out-of-order execution|out-of-order]] [[superscalar]] design. It can fetch 4 instructions per cycle. And{{clarify|date=September 2020}} rename and dispatch 4 Mops, and 8 |
The Cortex-A76 frontend is a 4-wide decode [[out-of-order execution|out-of-order]] [[superscalar]] design. It can fetch 4 instructions per cycle. And{{clarify|date=September 2020}} rename and dispatch 4 Mops, and 8 μops per cycle. The out-of-order window size is 128 entries. The backend is 8 execution ports{{clarify|date=September 2020}} with a pipeline depth of 13 stages and the execution latencies of 11 stages.<ref name="anand" /><ref>{{Cite web|date=2019-05-26|title=Arm Unveils Cortex-A77, Emphasizes Single-Thread Performance|url=https://fuse.wikichip.org/news/2339/arm-unveils-cortex-a77-emphasizes-single-thread-performance/|access-date=2020-06-18|website=WikiChip Fuse|language=en-US}}</ref> |
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The core supports [[Privilege (computing)|unprivileged]] 32-bit applications, but privileged applications must utilize the 64-bit [[ |
The core supports [[Privilege (computing)|unprivileged]] 32-bit applications, but privileged applications must utilize the 64-bit [[ARMv8-A]] [[instruction set architecture|ISA]].<ref name="the_reg">{{cite news |last1=Williams |first1=Chris |title=Arm emits Cortex-A76 – its first 64-bit-only CPU core (in kernel mode) |url=https://www.theregister.co.uk/2018/05/31/arm_cortex_a76/ |accessdate=1 June 2018 |publisher=The Register |date=31 May 2018}}</ref> It also supports Load acquire (LDAPR) instructions ([[ARM architecture#ARMv8.3-A|ARMv8.3-A]]), Dot Product instructions ([[ARMv8.4-A]]), PSTATE Speculative Store Bypass Safe (SSBS) bit and the speculation barriers (CSDB, SSBB, PSSBB) instructions ([[ARMv8.5-A]]).<ref>{{Cite web|url=http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.100798_0300_00_en/index.html|title=ARM documentation set for Cortex-A76|website=infocenter.arm.com|access-date=2019-06-15}}</ref> |
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Memory bandwidth increased 90% relative to the A75.<ref>{{cite news |last1=Armasu |first1=Lucian |title=Arm's Cortex-A76 Could Be The First True Challenger To x86 Chips On Laptops |url=https://www.tomshardware.com/news/cortex-76-high-laptop-performance,37158.html |accessdate=1 June 2018 |publisher=Tom's Hardware |date=31 May 2018}}</ref><ref>{{cite news |last1=Triggs |first1=Robert |title=Arm Cortex-A76 CPU deep dive |url=https://www.androidauthority.com/cortex-a76-deep-dive-870896/ |accessdate=1 June 2018 |publisher=Android Authority |date=31 May 2018}}</ref> According to ARM, the A76 is expected to offer twice the performance of an A73 and is targeted beyond mobile workloads. The performance is targeted at "[[laptop class]]", including [[Windows 10]] devices,<ref>{{cite news |last1=Hruska |first1=Joel |title= |
Memory bandwidth increased 90% relative to the A75.<ref>{{cite news |last1=Armasu |first1=Lucian |title=Arm's Cortex-A76 Could Be The First True Challenger To x86 Chips On Laptops |url=https://www.tomshardware.com/news/cortex-76-high-laptop-performance,37158.html |accessdate=1 June 2018 |publisher=Tom's Hardware |date=31 May 2018}}</ref><ref>{{cite news |last1=Triggs |first1=Robert |title=Arm Cortex-A76 CPU deep dive |url=https://www.androidauthority.com/cortex-a76-deep-dive-870896/ |accessdate=1 June 2018 |publisher=Android Authority |date=31 May 2018}}</ref> According to ARM, the A76 is expected to offer twice the performance of an A73 and is targeted beyond mobile workloads. The performance is targeted at "[[laptop class]]", including [[Windows 10]] devices,<ref>{{cite news |last1=Hruska |first1=Joel |title=ARM's New Cortex-A76 SoC Targets Windows Laptop Market |url=https://www.extremetech.com/mobile/270362-arm-cortex-a76-targets-laptop-market |accessdate=1 June 2018 |publisher=Extreme Tech |date=31 May 2018}}</ref> competitive with [[Intel]]'s [[Kaby Lake]].<ref>{{cite news |last1=Bright |first1=Peter |title=ARM promises laptop-level performance in 2019 |url=https://arstechnica.com/gadgets/2018/06/arm-promises-laptop-level-performance-in-2019/ |accessdate=1 June 2018 |publisher=Ars Technica |date=1 June 2018}}</ref> |
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The Cortex-A76 support [[ARM DynamIQ|ARM's DynamIQ]] technology, expected to be used as high-performance cores when used in combination with [[ARM_Cortex-A55|Cortex-A55]] power-efficient cores.<ref name="anand" /> |
The Cortex-A76 support [[ARM DynamIQ|ARM's DynamIQ]] technology, expected to be used as high-performance cores when used in combination with [[ARM_Cortex-A55|Cortex-A55]] power-efficient cores.<ref name="anand" /> |
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==Licensing== |
==Licensing== |
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The Cortex-A76 is available as [[Semiconductor intellectual property core|SIP core]] to licensees, and its design makes it suitable for integration with other SIP cores (e.g. [[Graphics processing unit|GPU]], [[display controller]], [[Digital signal processor|DSP]], [[image processor]], etc.) into one [[Die (integrated circuit)|die]] constituting a [[system on a chip]] (SoC). |
The Cortex-A76 is available as a [[Semiconductor intellectual property core|SIP core]] to licensees, and its design makes it suitable for integration with other SIP cores (e.g. [[Graphics processing unit|GPU]], [[display controller]], [[Digital signal processor|DSP]], [[image processor]], etc.) into one [[Die (integrated circuit)|die]] constituting a [[system on a chip]] (SoC). |
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== Usage == |
== Usage == |
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The Cortex-A76 was first used in the [[HiSilicon#Kirin 980 |
The Cortex-A76 was first used in the [[HiSilicon#Kirin 980 and Kirin 985 5G/4G|HiSilicon Kirin 980]].<ref>{{Cite web|last=Frumusanu|first=Andrei|title=HiSilicon Announces The Kirin 980: First A76, G76 on 7nm|url=https://www.anandtech.com/show/13298/hisilicon-announces-the-kirin-980-first-a76-g76-on-7nm|access-date=2020-11-13|website=www.anandtech.com}}</ref> |
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ARM has also collaborated with Qualcomm for a semi-custom version of the Cortex-A76, used within their high-end [[Kryo#Kryo 495|Kryo 495]] (Snapdragon 8cx)/[[Kryo#Kryo 485|Kryo 485]] (Snapdragon 855 and 855 Plus), and also in their mid-range [[Kryo#Kryo 460|Kryo 460]] (Snapdragon 675) and [[Kryo#Kryo 470|Kryo 470]] (Snapdragon 730) CPUs. One of the modifications Qualcomm made was increasing reorder buffer to increase the out-of-order window size.<ref>{{Cite web|url=https://www.anandtech.com/show/14384/arm-announces-cortexa77-cpu-ip|title=Arm's New Cortex-A77 CPU Micro-architecture: Evolving Performance|last=Frumusanu|first=Andrei|website=www.anandtech.com|access-date=2019-06-16}}</ref> |
ARM has also collaborated with Qualcomm for a semi-custom version of the Cortex-A76, used within their high-end [[Kryo#Kryo 495|Kryo 495]] (Snapdragon 8cx)/[[Kryo#Kryo 485|Kryo 485]] (Snapdragon 855 and 855 Plus), and also in their mid-range [[Kryo#Kryo 460|Kryo 460]] (Snapdragon 675) and [[Kryo#Kryo 470|Kryo 470]] (Snapdragon 730) CPUs. One of the modifications Qualcomm made was increasing reorder buffer to increase the out-of-order window size.<ref>{{Cite web|url=https://www.anandtech.com/show/14384/arm-announces-cortexa77-cpu-ip|title=Arm's New Cortex-A77 CPU Micro-architecture: Evolving Performance|last=Frumusanu|first=Andrei|website=www.anandtech.com|access-date=2019-06-16}}</ref> |
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It is also used in the [[Exynos#Exynos 900 series|Exynos 990]] and Exynos Auto V9 |
It is also used in the [[Exynos#Exynos 900 series|Exynos 990]] and Exynos Auto V9,<ref>{{Cite web|title=Exynos 990 Mobile Processor: Specs, Features {{!}} Samsung Exynos|url=https://www.samsung.com/semiconductor/minisite/exynos/products/mobileprocessor/exynos-990/|access-date=2020-06-18|website=Samsung Semiconductor|language=en}}</ref> the [[List of MediaTek systems on chips#Helio G Series (2019–present)|MediaTek Helio G90/G90T/G95/G99]] and [[List of MediaTek systems on chips#Dimensity 800 Series|Dimensity 800 and Dimensity 820]], and the [[HiSilicon#Kirin 980 and Kirin 985 5G/4G|HiSilicon Kirin 985 5G]] and [[HiSilicon#Kirin 990 4G, Kirin 990 5G and Kirin 990E 5G|Kirin 990 4G/990 5G/990E 5G]].<ref>{{Cite web|last=MediaTek|date=2020-06-18|title=MediaTek Helio G90 Series|url=https://www.mediatek.com/products/smartphones/mediatek-helio-g90-series|access-date=2020-06-18|website=MediaTek|language=en}}</ref><ref>{{Cite web|last=MediaTek|date=2020-06-18|title=MediaTek Dimensity 800|url=https://www.mediatek.com/products/smartphones/dimensity-800|access-date=2020-06-18|website=MediaTek|language=en}}</ref><ref>{{Cite web|last=MediaTek|date=2020-06-18|title=MediaTek Dimensity 820|url=https://www.mediatek.com/products/smartphones/dimensity-820|access-date=2020-06-18|website=MediaTek|language=en}}</ref> |
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The Cortex-A76 can be found in [[Snapdragon 855]] as Big-core. |
The Cortex-A76 can be found in [[Snapdragon 855]] as Big-core. |
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The Cortex-A76 is used as Big-core in [[Intel]] Agilex D-series SoC FPGA devices.<ref>{{Cite web|title=Intel Agilex D-Series FPGA White Paper|author=Mark van der Zalm|url=https://www.intel.com/content/www/us/en/products/docs/programmable/agilex-d-series-fpga-whitepaper.html|website=Intel|access-date=2022-10-20}}</ref> |
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In September 2023, the [[Raspberry Pi]] 5 was introduced with a [[Broadcom]] BCM2712 quad-core Arm Cortex-A76 processor with a clock speed of 2.4 GHz.<ref>{{Cite web|title=Introducing: Raspberry Pi 5!|author=Eben Upton|url=https://www.raspberrypi.com/news/introducing-raspberry-pi-5/|website=Raspberry Pi|access-date=2023-10-21}}</ref> |
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== See also == |
== See also == |
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{{Application ARM-based chips}} |
{{Application ARM-based chips}} |
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[[Category:ARM |
[[Category:ARM processors]] |
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[[Category:Microarchitectures]] |
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Latest revision as of 01:40, 13 June 2024
| General information | |
|---|---|
| Launched | 2018[1] |
| Designed by | ARM Holdings |
| Performance | |
| Max. CPU clock rate | to 3.0 GHz in phones and 3.3 GHz in tablets/laptops |
| FSB speeds | 100 to 104 |
| Address width | 40-bit |
| Cache | |
| L1 cache | 128 KiB (64 KiB I-cache with parity, 64 KiB D-cache) per core |
| L2 cache | 128–512 KiB per core |
| L3 cache | 512 KiB–4 MiB (optional) |
| Architecture and classification | |
| Microarchitecture | ARM Cortex-A76 |
| Instruction set | ARMv8-A: A64, A32, and T32 (at the EL0 only) |
| Extensions | |
| Physical specifications | |
| Cores |
|
| Co-processor | ARM Cortex-A55 (optional) |
| Products, models, variants | |
| Product code name |
|
| Variant | |
| History | |
| Predecessors | ARM Cortex-A75 ARM Cortex-A73 ARM Cortex-A72 |
| Successor | ARM Cortex-A77 |
The ARM Cortex-A76 is a central processing unit implementing the ARMv8.2-A 64-bit instruction set designed by ARM Holdings' Austin design centre. ARM states a 25% and 35% increase in integer and floating point performance, respectively, over a Cortex-A75 of the previous generation.[2]
Design[edit]
The Cortex-A76 serves as the successor of the ARM Cortex-A73 and ARM Cortex-A75, though based on a clean sheet design.
The Cortex-A76 frontend is a 4-wide decode out-of-order superscalar design. It can fetch 4 instructions per cycle. And[clarification needed] rename and dispatch 4 Mops, and 8 μops per cycle. The out-of-order window size is 128 entries. The backend is 8 execution ports[clarification needed] with a pipeline depth of 13 stages and the execution latencies of 11 stages.[2][3]
The core supports unprivileged 32-bit applications, but privileged applications must utilize the 64-bit ARMv8-A ISA.[4] It also supports Load acquire (LDAPR) instructions (ARMv8.3-A), Dot Product instructions (ARMv8.4-A), PSTATE Speculative Store Bypass Safe (SSBS) bit and the speculation barriers (CSDB, SSBB, PSSBB) instructions (ARMv8.5-A).[5]
Memory bandwidth increased 90% relative to the A75.[6][7] According to ARM, the A76 is expected to offer twice the performance of an A73 and is targeted beyond mobile workloads. The performance is targeted at "laptop class", including Windows 10 devices,[8] competitive with Intel's Kaby Lake.[9]
The Cortex-A76 support ARM's DynamIQ technology, expected to be used as high-performance cores when used in combination with Cortex-A55 power-efficient cores.[2]
Licensing[edit]
The Cortex-A76 is available as a SIP core to licensees, and its design makes it suitable for integration with other SIP cores (e.g. GPU, display controller, DSP, image processor, etc.) into one die constituting a system on a chip (SoC).
Usage[edit]
The Cortex-A76 was first used in the HiSilicon Kirin 980.[10]
ARM has also collaborated with Qualcomm for a semi-custom version of the Cortex-A76, used within their high-end Kryo 495 (Snapdragon 8cx)/Kryo 485 (Snapdragon 855 and 855 Plus), and also in their mid-range Kryo 460 (Snapdragon 675) and Kryo 470 (Snapdragon 730) CPUs. One of the modifications Qualcomm made was increasing reorder buffer to increase the out-of-order window size.[11]
It is also used in the Exynos 990 and Exynos Auto V9,[12] the MediaTek Helio G90/G90T/G95/G99 and Dimensity 800 and Dimensity 820, and the HiSilicon Kirin 985 5G and Kirin 990 4G/990 5G/990E 5G.[13][14][15]
The Cortex-A76 can be found in Snapdragon 855 as Big-core.
The Cortex-A76 is used as Big-core in Intel Agilex D-series SoC FPGA devices.[16]
In 2020 Cortex-A76 was used in Rockchip RK3588 and RK3588s.
In September 2023, the Raspberry Pi 5 was introduced with a Broadcom BCM2712 quad-core Arm Cortex-A76 processor with a clock speed of 2.4 GHz.[17]
See also[edit]
- ARM Cortex-A75, predecessor
- ARM Cortex-A77, successor
- Comparison of ARMv8-A cores, ARMv8 family
References[edit]
- ^ Shrout, Ryan; Moorhead, Patrick (31 May 2018). "Ep 23 - 5/31/18 - The Future of Arm with Nandan Nayampally". The Tech Analysts Podcast. Retrieved 1 June 2018.
- ^ a b c Frumusanu, Andrei (31 May 2018). "Arm Cortex-A76 CPU Unveiled". Anandtech. Retrieved 1 June 2018.
- ^ "Arm Unveils Cortex-A77, Emphasizes Single-Thread Performance". WikiChip Fuse. 2019-05-26. Retrieved 2020-06-18.
- ^ Williams, Chris (31 May 2018). "Arm emits Cortex-A76 – its first 64-bit-only CPU core (in kernel mode)". The Register. Retrieved 1 June 2018.
- ^ "ARM documentation set for Cortex-A76". infocenter.arm.com. Retrieved 2019-06-15.
- ^ Armasu, Lucian (31 May 2018). "Arm's Cortex-A76 Could Be The First True Challenger To x86 Chips On Laptops". Tom's Hardware. Retrieved 1 June 2018.
- ^ Triggs, Robert (31 May 2018). "Arm Cortex-A76 CPU deep dive". Android Authority. Retrieved 1 June 2018.
- ^ Hruska, Joel (31 May 2018). "ARM's New Cortex-A76 SoC Targets Windows Laptop Market". Extreme Tech. Retrieved 1 June 2018.
- ^ Bright, Peter (1 June 2018). "ARM promises laptop-level performance in 2019". Ars Technica. Retrieved 1 June 2018.
- ^ Frumusanu, Andrei. "HiSilicon Announces The Kirin 980: First A76, G76 on 7nm". www.anandtech.com. Retrieved 2020-11-13.
- ^ Frumusanu, Andrei. "Arm's New Cortex-A77 CPU Micro-architecture: Evolving Performance". www.anandtech.com. Retrieved 2019-06-16.
- ^ "Exynos 990 Mobile Processor: Specs, Features | Samsung Exynos". Samsung Semiconductor. Retrieved 2020-06-18.
- ^ MediaTek (2020-06-18). "MediaTek Helio G90 Series". MediaTek. Retrieved 2020-06-18.
- ^ MediaTek (2020-06-18). "MediaTek Dimensity 800". MediaTek. Retrieved 2020-06-18.
- ^ MediaTek (2020-06-18). "MediaTek Dimensity 820". MediaTek. Retrieved 2020-06-18.
- ^ Mark van der Zalm. "Intel Agilex D-Series FPGA White Paper". Intel. Retrieved 2022-10-20.
- ^ Eben Upton. "Introducing: Raspberry Pi 5!". Raspberry Pi. Retrieved 2023-10-21.